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Browse Prior Art Database

Local Address Circuit for SRAM

IP.com Disclosure Number: IPCOM000121329D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Girard, P: AUTHOR

Abstract

Disclosed is a CMOS circuit that generates a short output pulse from true and complement signals delivered by a conventional input buffer. This pulse realizes a local address transition detection as it is often used in stand-alone static SRAM. This circuit offers a fast response to input transition because it uses pass-gate transistors. Output pulse width is determined by internal delays and cross coupling between the two input phases.

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Local Address Circuit for SRAM

      Disclosed is a CMOS circuit that generates a short output
pulse from true and complement signals delivered by a conventional
input buffer.  This pulse realizes a local address transition
detection as it is often used in stand-alone static SRAM.  This
circuit offers a fast response to input transition because it uses
pass-gate transistors.  Output pulse width is determined by internal
delays and cross coupling between the two input phases.

      A schematic diagram of the circuit is shown in the figure.  The
circuit is made of two N-type field-effect transistors (FETs) with
their drain tied together to the output node (named AX).  Their
sources are connected to each of the input signals (AA and AB).  Two
delay chains, made of two inverters (I1 and I2 for the first chain
and I3 and I4 for the second one), are introduced between input
signals (AA and AB) and gates of pass-gate transistors (respectively,
T2 and T1).

      The behavior of the circuit will be explained for one
transition of input signals, the other transition is leading to the
same analysis due to the symmetrical look of the circuit. At the
beginning, it is assumed that signal at node AA is low and signal at
node AB is high.  Accordingly, signal at node 1 is high and signal at
node 2 is low.  Thus, before the transition of input signals AA and
AB occurs, the NFET transistor T1 is ON and transistor T2 is OFF.
Therefore, output node AX is low because AA is...