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Browse Prior Art Database

Test Case Portability Method for Micro Channel Personal Computers

IP.com Disclosure Number: IPCOM000121330D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 90K

Publishing Venue

IBM

Related People

Kalman, DA: AUTHOR [+3]

Abstract

Described is a test case portability software method for personal computers equipped with the Micro Channel*. The method provides the ability to port simulation test cases to different simulation models equipped with processors, such as the Intel 80186 and 80376.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test Case Portability Method for Micro Channel Personal Computers

      Described is a test case portability software method for
personal computers equipped with the Micro Channel*.  The method
provides the ability to port simulation test cases to different
simulation models equipped with processors, such as the Intel 80186
and 80376.

      Typically, the method involves circuit chip sets that interface
to the Micro Channel.  The chip sets are equipped with an Intel 80186
or an 80376 processor.  In prior art, to simulate a chip set, models
were written to simulate the 80186, 80376 and the Micro Channel bus
cycles.  Test cases were then used to instruct the model of the type
of bus cycle desired. The circuit chip sets use a logic simulator for
function verification and a timing simulator for timing verification.
Models were written for both simulators because the model language
was not compatible between the two simulators.  The concept described
herein allows the circuit chip sets to use only one set of simulation
test cases which then can be ported to either simulator.  Since the
chip sets have over fifty extensive test cases, this greatly reduces
the test case development time.

      The following illustrates how a common test case interface can
be used across different simulators:

      Command, address, and data are variables that are loaded by the
test case.  The test case then calls a routine to load these
variables into the simulation models internal command, address, and
data buffers.  The routine to load these variables has to be unique
for each simulation environment since the internal arrays are
accessed differently between each simulator.  After the model is
loaded with the command, address, and data, the test case then tells
the model to start executing the command.  This can be done with a
simple trigger input to the model.  If the input is a one, the model
will start executing the commands in the command buffer.

      An example of a test case that does a one-byte write and read
from memory is as follows:
         /* Do write operation,*/
         COMMAND := B'1110...