Browse Prior Art Database

Micro Channel Planar to Adapter Card Interrupt Redirection

IP.com Disclosure Number: IPCOM000121346D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+4]

Abstract

Disclosed is a method for implementing a Micro Channel* busmaster card that contains an Intel processor which requires access to system interrupts but does not in itself contain any standard interrupt controllers (i.e., Intel 8259's).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Micro Channel Planar to Adapter Card Interrupt Redirection

      Disclosed is a method for implementing a Micro Channel*
busmaster card that contains an Intel processor which requires access
to system interrupts but does not in itself contain any standard
interrupt controllers (i.e., Intel 8259's).

      The solution described herein to this need is to add some
minimal support logic that allows the busmaster adapter to mimic the
operation of an actual interrupt controller without the requirement
of actually using one.  The figure shows one possible hardware
embodiment of the logic required to allow the upgrade processor to
perform an actual interrupt cycle generated without the
before-mentioned interrupt controllers.
Interrupt Redirection Hardware Diagram
     (a) Micro Channel
     (b) Micro Channel I/O Decode Circuitry
          1:Control Inputs, 2:Address Inputs, 3:Interrupt
          Write Decode
          4:Interrupt Request Status Read Decode
     (c) Transceiver(s)
          1:Micro Channel Data, 2:Micro Channel R/W 3:Local
          Data, Status
            Data,
     (d) Latch
          1:Latch Enable, 2:Local Data (Interrupt Vector
          Number),
          3:Output Enable, 4:Processor Data
     (e)  Flip/Flop
          1:Clear, 2:Set, 3:INT_REQ
     (f)  Processor
          1:Processor Data, 2:Interrupt Acknowledge (see
          note),
          3:Processor INT Input
Note: INT_ACK is generated by decode circuitry external to the
processor by decoding the W/R, D/C, and M/IO along with A(2)
processor lines.
Method of Operation:

      Whenever an interrupt is required t...