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Logic And Circuit for Multi-bus Arbiter

IP.com Disclosure Number: IPCOM000121351D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Takayama, M: AUTHOR

Abstract

Disclosed is a logic of a multi-bus arbiter for a multi-CPU system. This logic of a multi-bus arbiter makes it easy to design a circuit where some input ports (for example, CPU) use one common Input/Output device or RAM by using a generalized Boolean algebra. The number of input ports is not limited logically. This logic can be applied to PLA (Programmable Logic Array) or gate-array.

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Logic And Circuit for Multi-bus Arbiter

      Disclosed is a logic of a multi-bus arbiter for a
multi-CPU system.  This logic of a multi-bus arbiter makes it easy to
design a circuit where some input ports (for example, CPU) use one
common Input/Output device or RAM by using a generalized Boolean
algebra.  The number of input ports is not limited logically.  This
logic can be applied to PLA (Programmable Logic Array) or gate-array.

      A priority level is to be adapted to each port.  Here, it is
denoted by 'n' and the smaller 'n' has the higher priority level.  A
request and an acknowledgement from each port are denoted by 'Rn' and
'An', respectively, and latch circuits for the respective input ports
to hold the state transition of the bus are denoted by 'Qn' and
'/Qn'.

      A basic circuit is shown in Fig. 1.

      When a port sends a request to a device and gets the right to
use the bus, it should have an acknowledgement returned.  If the
acknowledgement to the request is not returned, the ready state is
indicated and the wait signal to the port should be sent.  An example
of a wait circuit is shown in Fig. 2.

      This acknowledgement is returned to one input port, in case
other input ports do not use the bus.  Therefore, the acknowledgement
is expressed as follows:
      /An = ((k=1;PAI;N (/Qk)) / /Qn) & Qn & Rn          (1)
      PAI is function to define logical multiplication
      k=1;PAI;N (/Qk)  = /Q1 & /Q2 & /Q3 & ... & /QN-1 & /QN
where 'n' is priority and 'N' is the number of input ports. Input
c...