Browse Prior Art Database

Extendable Alert Register

IP.com Disclosure Number: IPCOM000121366D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 106K

Publishing Venue

IBM

Related People

Buckland, PA: AUTHOR [+4]

Abstract

A storage subsystem adapter supports a number of storage devices (DASD) that execute commands concurrently with multiple commands queued for each device. This article describes an Alert Register (AR) implementation which, used in conjunction with a Completion Register (described in [*], supports the reporting of asynchronous conditions, error conditions and exception status for commands.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Extendable Alert Register

      A storage subsystem adapter supports a number of storage
devices (DASD) that execute commands concurrently with multiple
commands queued for each device.  This article describes an Alert
Register (AR) implementation which, used in conjunction with a
Completion Register (described in [*], supports the reporting of
asynchronous conditions, error conditions and exception status for
commands.

      The exception reporting means must pass at least a 32-bit word
(4-byte) exception status to the host to preclude the need for
multiple bus accesses to resolve an interrupt.  For certain
interrupts, it is desirable to pass extended status of more than 4
bytes.  This article describes an AR mechanism capable of passing 4,
8, 12 or 16 bytes of error status.  The length of each status posting
is passed to the Device Driver (DD) through special error codes
posted in the Completion Register (CR) in place of the usual tags.
The DD reads only the exact length of error status specified by the
error code, thus improving bus throughput.

      The Status Control Register (STATCTL) is common with the CR.
Figure A shows the subset bits of the STATCTL Register that are
unique to this disclosure, omitting those bits covered by [*].
Figure B shows the arrangement of valid Alert status words in the
Alert Register RAM space addressable from the Micro Channel*.  The
right-hand 32-bit Alert word (Figure C) is always valid and contains
the basic Alert identification information (tag, address, alert
type). Byte 0 contains a tag (see [*]) or a special code indicating
the type of interrupt.  Byte 2 contains an adapter error code with
the code point 0x00 signifying no adapter error. Bytes 1 and 3 are
variously interpreted according to the context provided by bytes 0
and 2.

      As AR is read by the host, the last word read is reflected in
a Backup Register to prevent volatile data from being lost in the
event of a bus error during the transfer.  By placing the vital data
in the last word, we are assured that the vital data...