Browse Prior Art Database

Optimized Clock Generation for CMOS VLSI Chips

IP.com Disclosure Number: IPCOM000121367D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Stacy, K: AUTHOR

Abstract

Inaccurate and variable delay lines used in clock generation internal to CMOS VLSI chips are eliminated by a proper split of the clock generation circuitry internal and external to the chips. Designing the portion of the external clock generation circuitry with rising edge- triggered logic significantly reduces sensitivity to oscillator duty cycle. The figure shows a sample implementation of this clock generation scheme. The extra reset logic guarantees that the shift registers are not clocked during reset and is pertinent only to this sample implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Optimized Clock Generation for CMOS VLSI Chips

      Inaccurate and variable delay lines used in clock
generation internal to CMOS VLSI chips are eliminated by a proper
split of the clock generation circuitry internal and external to the
chips.  Designing the portion of the external clock generation
circuitry with rising edge- triggered logic significantly reduces
sensitivity to oscillator duty cycle.  The figure shows a sample
implementation of this clock generation scheme.  The extra reset
logic guarantees that the shift registers are not clocked during
reset and is pertinent only to this sample implementation.

      This clock generation scheme minimizes the use of external
bipolar circuitry by generating only a basic clock framework external
to the CMOS VLSI chip, and then modifying this clock framework inside
the CMOS VLSI chip to obtain the proper timings.  The basic clock
framework is a ring counter.  The ring counter signals are sent to
the CMOS VLSI chip, which uses simple XOR circuits to generate the
various clock pulses required.

      No delay lines are needed in the CMOS VLSI for shaping clock
pulses by clock chopping their rising or falling edges.  These delay
lines have a wide variation of delay from minimum to maximum, thereby
creating a wide variation in the timings of the circuits using them.
Another benefit gained from the elimination of the delay lines is
increased testability of the internal clock generation circuitry.
Designing cloc...