Browse Prior Art Database

Automatic Multiplexer for IDD Peak Detector

IP.com Disclosure Number: IPCOM000121368D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

DeBar, DE: AUTHOR [+3]

Abstract

There is much interest in the VLSI industry in being able to detect Idd peak current transients. Typically, there are two Idd paths provided to the Device Under Test (DUT). The first is Idd internal which supplies all combinatorial logic and latches. A second Idd path supplies current for all off-chip drivers. The two are separated to prevent noise coupling from one to the other. There is interest in knowing the peak current in both paths. This invention teaches how to multiplex the output from two analog peak detectors into one digital peak detector. The multiplexing is done in such a way as to provide three modes of operation, all under Automated Test Equipment (ATE) control. The first mode is the automatic mode in which the multiplexer will automatically select whichever analog peak detector is at the higher voltage.

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Automatic Multiplexer for IDD Peak Detector

      There is much interest in the VLSI industry in being able
to detect Idd peak current transients.  Typically, there are two Idd
paths provided to the Device Under Test (DUT).  The first is Idd
internal which supplies all combinatorial logic and latches.  A
second Idd path supplies current for all off-chip drivers.  The two
are separated to prevent noise coupling from one to the other.  There
is interest in knowing the peak current in both paths.  This
invention teaches how to multiplex the output from two analog peak
detectors into one digital peak detector.  The multiplexing is done
in such a way as to provide three modes of operation, all under
Automated Test Equipment (ATE) control. The first mode is the
automatic mode in which the multiplexer will automatically select
whichever analog peak detector is at the higher voltage.  The second
mode always selects Idd internal.  The third and final mode always
selects Idd external.

      Fig. 1 is the schematic drawing of the multiplexer circuit.
Threshold detector LM393 is connected to the outputs of both the Idd
internal analog detector depicted as INT and the output of the Idd
external analog detector depicted as EXT via resistors R4 and R3.
Resistor R5 provides pull-up for the output of the LM393.  R1, R3,
and C1 provide needed hysteresis to prevent oscillation when INT and
EXT are equal voltage.  The output of LM393 is a logical one when EXT
is greater than INT.  The output of LM393 is a logical zero when INT
is greater than EXT.  The three NOR gates...