Browse Prior Art Database

Completion Register

IP.com Disclosure Number: IPCOM000121371D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 139K

Publishing Venue

IBM

Related People

Buckland, PA: AUTHOR [+3]

Abstract

A storage subsystem adapter supports a number of storage devices that can execute commands concurrently with multiple commands queued for each storage device. This article describes a Completion Register (CR) implementation which, when used in conjunction with an Alert Register (described IN ([*]) SUPPORTS THE REPORTING ON TERMINAL STATUS FOR commands.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Completion Register

      A storage subsystem adapter supports a number of storage
devices that can execute commands concurrently with multiple commands
queued for each storage device.  This article describes a Completion
Register (CR) implementation which, when used in conjunction with an
Alert Register (described IN ([*]) SUPPORTS THE REPORTING ON TERMINAL
STATUS FOR commands.

      When the host issues a command to the subsystem, it assigns an
unique 1-byte tag to the command in the range 0x01...0x7F.  When a
command completes successfully, the subsystem microcode returns the
corresponding tag in CR.  The act of writing CR hardware interrupts
the host.  The host reads the CR to determine which command(s)
completed.  The act of reading CR resets the hardware interrupt.
During intensive activity, several commands may complete before the
host reads CR; therefore, CR is 4 bytes wide so that up to four
completions may be reported with a single host interrupt.

      Special codes can be posted in CR to indicate exception
conditions as defined in the separate article on Alert Register.
Completed tags are inserted in CR bytes from high- to low-order byte
(left-to-right) as commands complete.  Unused bytes contain the
reserved tag 0x00.  The host processes tags in successive bytes until
the register is exhausted or a zero terminator is encountered.  If
more than four commands complete before the host reads the CR, then
the remaining tags are queued by the adapter microcode until the
register is read by the host.

      Fig. 1 shows the 4-byte CR along with the Validity Gating
controlled by CR_Gate that connects it to the host interface.  Fig. 2
shows the Status Control (STATCTL) Register and combinatorial logic
which is the synchronizing interface between the host and the adapter
microcode.

      STATCTL bits are variously controlled by hardware and software.
Each bit is described in detail below.  The arrows indicate flow of
information for each bit of STATCTL (i.e., an arrow from microcode to
a STATCTL bit indicates that that bit can be directly affected by
writing the register from microcode).  When the CR_Gate is not
active, the CR is hidden from the host and an all-zero word is
returned if the host attempts to read the register.  Since the action
of the host reading the register resets the CR_Gate bit, the host can
read the register contents only once without action by the microcode
to make CR_Gate active again.  This mechanism prevents the host from
reading a tag multiple times.
     CR_Gate Set by the microcode and reset by hardware.
     When the host reads CR, this bit is reset, making the
     register appear to the host to contain all zeroes.
     CR_Gate determines whether a microcode write into the
     CR sets CR_Valid and interrupts the host (no gate - no
     valid; no gate - no interrupt).
     CR_Valid Set by hardware and read by microcode.  This
     bit is fee...