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Novel Methodology for Contacting Polysilicon Gates

IP.com Disclosure Number: IPCOM000121383D
Original Publication Date: 1991-Aug-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Gould, SW: AUTHOR [+4]

Abstract

By redefining allowable positions for logic service terminals (LSTs) to field-effect transistor (FET) gates, increased device gate width becomes available and complexity of device interconnection is reduced. Thus, improved device yield and density is achieved.

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Novel Methodology for Contacting Polysilicon Gates

      By redefining allowable positions for logic service terminals
(LSTs) to field-effect transistor (FET) gates, increased device gate
width becomes available and complexity of device interconnection is
reduced.  Thus, improved device yield and density is achieved.

      Referring to the figure, gate widths wn and wp of NFETs and
PFETs, respectively, have been limited by constraining allowable LST
contact positions to 1,2,3, or 4.  In the new methodology, contact
may be made to any of the contact positions shown, thereby increasing
possible gate width to Wn and Wp.  In the new method, thick
insulation formation is delayed until after gate wiring completion.

      By providing this increased choice of gate connection positions
to designers of logic books, connection from a gate to a next device
contact may be made in many cases by a straight wiring line within a
single wiring level.  Old connection position constraints often
incurred the need for two levels of wiring and two or more via
connections; thus, there is reduced probability of bad contacts and
less space is occupied by wiring and vias.

      Disclosed anonymously.