Browse Prior Art Database

Internal Performance Measurement Counters

IP.com Disclosure Number: IPCOM000121447D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bahr, JE: AUTHOR [+5]

Abstract

A method to simultaneously count a variety of hardware events or events duration not accessible externally using a limited number and size of internal hardware counters causing negligible system perturbation is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Internal Performance Measurement Counters

      A method to simultaneously count a variety of hardware
events or events duration not accessible externally using a limited
number and size of internal hardware counters causing negligible
system perturbation is disclosed.

      This invention used a hybrid hardware/microcode implementation
which uses a limited set and size of internal hardware counters to
actually count events, and then microcode to accumulate the counts in
Main Storage.  The hardware implementation reduces the perturbation
to executing processes.  The microcode implementation reduces
hardware complexity and impact to cell counts.  The hardware counters
are programmable and capable of counting any number of hardware
events.  Event subsets can also be counted by using an event criteria
compare register.  The microcode is also capable of timeslicing the
event's hardware counts, thus allowing a small number of hardware
counters to be multiplexed, permitting the counting of many events
simultaneously.

      The actual counting of hardware events or event duration (the
number of cycles during which a condition is true) is done using
internal hardware counters.  Most of the events of interest are only
accessible internally.  A limited set and size of internal counters
are used for the least impact on hardware cell counts.  The hardware
counters do not impact performance, as they run in parallel with
event generation.  Only when the counters ar...