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Browse Prior Art Database

BiCMOS Logic Circuits Using Emulated PNP Transistor

IP.com Disclosure Number: IPCOM000121460D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Shin, HJ: AUTHOR

Abstract

Disclosed are new npn-only BiCMOS logic circuits where drivers effectively operate in the push-pull, pseudo emitter-follower mode. The new circuits utilize an emulated-pnp transistor which is a combination of a p-channel JFET (Junction Field-Effect Transistor) and an npn BJT (Bipolar Junction Transistor) easily realizable in any npn bipolar technology.

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This is the abbreviated version, containing approximately 52% of the total text.

BiCMOS Logic Circuits Using Emulated PNP Transistor

      Disclosed are new npn-only BiCMOS logic circuits where
drivers effectively operate in the push-pull, pseudo emitter-follower
mode.  The new circuits utilize an emulated-pnp transistor which is a
combination of a p-channel JFET (Junction Field-Effect Transistor)
and an npn BJT (Bipolar Junction Transistor) easily realizable in any
npn bipolar technology.

      Fig. 1 shows the first new circuit that consists of a CMOS
logic stage (MN1-MN2 and MP1-MP2) and a push-pull driver stage (QN1
and QP1-QN2).  The combination of the p-JFET QP1 and npn-BJT QN2 is
the emulated-pnp.  When the gate potential of QP1 is lower than the
source potential by the turn-on voltage, QP1 conducts to provide a
current into the base of QN2 and b times the current flows through
the collector of QN2. In effect, the gate of QP1 may be considered as
the base of an equivalent pnp-BJT, the common node (source of QP1 and
collector of QN2), as the emitter, and the emitter of QN2, as the
collector.  The p-JFET is implemented free in any npn bipolar
technologies, and, furthermore, the p-JFET/npn-BJT combination can be
physically merged into one compact device with reduced area and
parasitics [*].

      If any input is '0', the node X is at VDD and the output
O is at VDD - VBE.  Because the gate-source bias of QP1 is VBE, as
long as its turn-on voltage is lower than VBE, the QP1-QN2 pair will
be OFF.  When both inputs are changed to '1', X falls rapidly turning
QN1 off and QP1-QN2 on.  The output then follows X through the
source-follower action of QP1 or pseudo emitter-follower action of
QP1-QN2. During the transient, if X is below O by more than VBE, the
gate junction of QP1 will be forward-biased and O will be discharged
more quickly.  The final output level will not go below VBE because
QN2 will be effectively OFF although QP1 is still ON.  If...