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Test Access Control Bus for VLSI Chips in an LSSD Design

IP.com Disclosure Number: IPCOM000121467D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Hajdu, J: AUTHOR [+3]

Abstract

Access to VLSI components in high level packages (MCM (multichip module), card, system) for testing is made by a test access control bus (TACB) to which each chip is connected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Test Access Control Bus for VLSI Chips in an LSSD Design

      Access to VLSI components in high level packages (MCM
(multichip module), card, system) for testing is made by a test
access control bus (TACB) to which each chip is connected.

      Fig. 1 shows the access scheme.  All chips are in star
configuration.  The TACB signals of Fig. 1 are defined as follows:
      -    LSSD clocks 1,2,...,n
           These clocks are normal (A-, B-) shift clocks used in LSSD
(level-sensitive scan design).  For the signal TM = 0 (inactive), the
logical values at scan-in are clocked into those chips to which shift
clocks are applied.  Individual scan clock signals allow each chip to
be initialized with different (test) data and to read out any test
responses.  The clocks of the different chips may also be
simultaneously activated, as is necessary, for instance, for the
parallel self-testing of all chips.
      -    SCAN-IN
           This signal represents the LSSD scan-in signal and is
common to all chips.
      -    SCAN-OUT 1,2,...,m
           These are the LSSD scan-out signals.  An LSSD scan-out
signal is unique to each chip and allows parallel monitoring of one
bit each of the various chips.  In some processors this feature is
used for signature checking after completion of testing.
      -    Test Mode (TM)
           TM selects any test mode.  While the test mode is active
(TM = 1), a TIR...