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Polysilicon Gate Process With Adjustable Gate Length

IP.com Disclosure Number: IPCOM000121471D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Koblinger, O: AUTHOR

Abstract

It is known to produce polysilicon gates of 0.4 mm width and less by MLR (multilayer resist) bias etching. The main difficulty with this process, however, is that the gate widths obtained may be too small because the initial dimensions in the resist have been too small or the bias etch step has been too long.

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Polysilicon Gate Process With Adjustable Gate Length

      It is known to produce polysilicon gates of 0.4 mm width
and less  by  MLR  (multilayer  resist) bias etching.   The main
difficulty with this process, however, is    that  the  gate widths
obtained  may  be  too  small  because  the  initial dimensions in
the resist have been too  small  or  the  bias etch step has been too
long.

      The  following  approach  seems  to   be   practicable,
considering  that the width of deposited (polysilicon) films can be
very accurately measured.

      Initially, the known MLR bias etch process is  used  to produce
first  structures  in  polysilicon  (Figs. 1A, 1B), taking care that
the line width is smaller than the  desired one.    (If  the  desired
value is, for example, 0.3 mm, the initial line width should be,  for
instance,  0.2  mm,  as, otherwise,  variations in the initial
tolerances may lead to line widths exceeding 0.3 mm in some wafer
regions.)

      After the polysilicon has been etched  (Fig.  1B),  the line
width (bias) is very accurately measured by electrical means.  The
measured value serves as a standard to determine the thickness of a
polysilicon layer to be  deposited  in  a further  process  step.
If the mean initial line width is, for example, 0.25 mm, an
additional  polysilicon  layer  of 0.031  mm  will  have  to  be
applied by LPCVD (low-pressure chemical vapor depositio...