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Level Down Converter for BiCMOS Circuits

IP.com Disclosure Number: IPCOM000121479D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

A level-shifted BiCMOS circuit can provide better circuit speed as compared to a pure CMOS circuit when driving a heavy capacitance load [*]. A level-shifted (LS) circuit, either a LS-BiCMOS or a LS-CMOS circuit, generates an output having a low level of one Vbe above Vss (Fig. 1). A level-shifted signal should be shifted down properly for non-shifted CMOS circuits in order to achieve CMOS-like gate-drive and noise margin.

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Level Down Converter for BiCMOS Circuits

      A level-shifted BiCMOS circuit can provide better circuit
speed as compared to a pure CMOS circuit when driving a heavy
capacitance load [*].  A level-shifted (LS) circuit, either a
LS-BiCMOS or a LS-CMOS circuit, generates an output having a low
level of one Vbe above Vss (Fig. 1).  A level-shifted signal should
be shifted down properly for non-shifted CMOS circuits in order to
achieve CMOS-like gate-drive and noise margin.

      Shown in Fig. 2 is a new level-down-converter (LDC), which
shifts down the output of a LS-CMOS (or LS-BiCMOS) circuit by one
Vbe.  The output swing of the LS-CMOS at node b is from Vdd to (Vss
+ Vbe), while the swing of the LDC output at node f is from (Vdd
- Vbe) to Vss.  The LDC circuit has two CMOS stages:  an input stage
with three diodes (D1, D2 and D3), and an output stage with a
cross-coupled NFET pull-down (QP3, QN3 and QD).  The addition of the
diodes D1 and D2 is to reduce the operation voltage across the NFETs
(QN2, QN3, and QD) during pull-down, and similarly, the voltage
across the PFET (QP2) during pull-up.  The diode D3 is used to set
the cross-coupled NFETs during pull-up.  Detailed circuit operations
are explained in Figs. 3 and 4 for pull-down and pull-up,
respectively.

      Shown in Fig. 3 is the operation of the LDC circuit when input
making a transition to high at node a.  The turn-on of QN1 brings
node b to Vl (Z Vbe above Vss), which, in turn, turns-on QP2.  The
node c is then charged to Vdd, which is one Vbe higher than the CMOS
device maximum voltage Vh, i.e., (Vdd - Vbe).  The voltage at node d
and...