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Browse Prior Art Database

Pass Device Magnitude Comparator Cell

IP.com Disclosure Number: IPCOM000121482D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Nguyen, Q: AUTHOR [+2]

Abstract

Disclosed is a an area-efficient comparator circuit that compares the magnitude of two binary numbers. This small 4-device circuit makes the implementation of full associative cache LRU replacement array feasible and practical.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pass Device Magnitude Comparator Cell

      Disclosed is a an area-efficient comparator circuit that
compares the magnitude of two binary numbers.  This small 4-device
circuit makes the implementation of full associative cache LRU
replacement array feasible and practical.

      The conventional magnitude comparator is based on the addition
of 2 complement numbers and a check of the overflow for the output.
This requires a complex and slow adder. The other method uses a
full-blown Karnaugh map expansion for minterms.  This results in a
large layout.  The comparator in this disclosure is very simple:
only four devices per bit.  With this small number of devices per
bit, the circuit can be applied in an array environment, such as an
associative magnitude compare in the cache LRU replacement array.

      Fig. 1 shows the circuit diagram of the comparator of this
disclosure. The comparison is done on a per-bit basis. A 1-bit
comparator is composed of only four main N-channel devices.  The
checking starts from MSB to LSB.

      When Ai < Bi, node n1 is pulled down to GND with devices T3
and T4.  There is no need to interrogate further down to the next
lower- order bit.  The output will be low for Ai > Bi.

      When Ai > Bi, the two pass devices (T1 and T2) turn off.
Again, there is no need to compare the next lower bit. Node N1 is
pulled high by the load device.  The output will be high for Ai > Bi.
Node N1 is pulled down by devices T3 and T4.  If Bi < Ai, node
N1 is left high.

      When Bi = Ai, one of the two pass devices turns on for further
interrogation to the next lower-order bit.

      The same procedure is followed for the next lower-order bit
until the LSB.  If A = B, the compare line, node N1 and the output
will be high.

      Fig. 2 show...