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Silicon On Insulator Vertical Complementary Bipolar Device Structure

IP.com Disclosure Number: IPCOM000121486D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 5 page(s) / 172K

Publishing Venue

IBM

Related People

Li, GP: AUTHOR [+2]

Abstract

Described is a complementary bipolar structure built on silicon-on- insulator (SOI). Both vertical NPN and PNP transistors are formed on an insulator to provide low parasitic capacitance. The resulting device is less susceptible to the effects of alpha particles than would be a non-SOI structure.

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Silicon On Insulator Vertical Complementary Bipolar Device Structure

      Described is a complementary bipolar structure built on
silicon-on- insulator (SOI).  Both vertical NPN and PNP transistors
are formed on an insulator to provide low parasitic capacitance.  The
resulting device is less susceptible to the effects of alpha
particles than would be a non-SOI structure.

      Fig. 1 shows the basic structure of the SOI device. Both the
NPN and the PNP are isolated from the substrate wafer by the
insulator so as to facilitate the integration of high-speed vertical
NPN and high- speed vertical PNP. Figs. 2a to 2h are shown to provide
an outline of the process flow in the fabrication of the
complementary bipolar device on an insulator.  The process steps are
as follows:
      a)   Starting with the thick undoped (f) epi-on-n+ wafer, the
f-epi can be prone to low temperature and a reduced pressure system
to reduce the out-diffusion of n+.  Then zero-level alignment keys
are put down by etching a trench through the f-epi.  The n+
subcollector implant is then performed, and p+ subcollector formation
follows. A cross section of the device at this step is shown in Fig.
2a.
      b)   A deep trench can be formed at this step to cut through
the n+ - p+ region to provide device isolation.  Then the trench is
refilled by undoped silicon and chemical-mechanical (chem-mech)
polishing is used to planarize the surface.  The silicon surface is
then oxidized for thin oxide growth.  The cross-section of the device
at this step is shown in Fig.  2b.  It should be noted that if the
wafer-bonding (described in step c) does not involve excess thermal
cycling, the deep trench can also serve as an alignment mask, thereby
saving on step a above.
      c)   Using the usual wafer-bonding technique, bond a substrate
wafer on the top.  A cross-section of the device at this step is
shown in Fig. 2c.
      d)   Using a combination of chem-mech polishing and
preferential etching of the n+ technique, remove n+ - substrate.  The
cross-section of the device at this step is shown in Fig.  2d. Note
that, for convenience, the f-epi regions are now drawn facing up.
      e)   A shallow-trench field oxide is used to cover the top of
the deep trench.  Non-field oxide can also be used in place of the
shallow trench.  The cross-section of the device at this step is
shown in Fig. 2e.
      f)   The n+ collector for the n-p-n transistor and the p+
collector for the pnp transistor are...