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Parameter Optimization for 3 Layer Chip Wiring

IP.com Disclosure Number: IPCOM000121497D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Knigge, B: AUTHOR [+3]

Abstract

Wiring programs for VLSI chips use parameters (weighting factors) to select the best of several possible solutions. With three wiring layers, there is usually a bottleneck in one direction (here, in the vertical direction which is the preferred one for layer 2). For the remaining layers 1 and 3, "wrong way wiring" should be minimized to avoid small wiring pieces in the bottleneck (layer 2). This article describes parameter (edge weight) inequalities for Dijkstra-type routers which are used for most industrial VLSI wiring applications. It is shown that after detailed wiring the use of such parameters considerably reduces the number of overflows and thus the turn-around- time.

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Parameter Optimization for 3 Layer Chip Wiring

      Wiring programs for VLSI chips use parameters (weighting
factors) to select the best of several possible solutions. With three
wiring layers, there is usually a bottleneck in one direction (here,
in the vertical direction which is the preferred one for layer 2).
For the remaining layers 1 and 3, "wrong way wiring" should be
minimized to avoid small wiring pieces in the bottleneck (layer 2).
This article describes parameter (edge weight) inequalities for
Dijkstra-type routers which are used for most industrial VLSI wiring
applications.  It is shown that after detailed wiring the use of such
parameters considerably reduces the number of overflows and thus the
turn-around- time.

      A preferred direction is assigned to each layer.  In the
example, a horizontal direction is assigned to layers 1 and 3, and a
vertical one to layer 2.  This implies a lack of vertical wiring
channels compared to the horizontal channels available.

      The edge cost used for 1-channel wiring segments and vias
should meet the following conditions:
A)   1-channel jogs (jumps from one channel to another) should be
wired in a single plane.  The use of vias blocks one channel in
another layer without freeing any channels therein.
B)   Wiring a 2-channel jog in another layer frees one channel in
this layer, while blocking one channel in the other layer.  As there
are fewer vertical channels (layer 2), 2-channel jogs in layers 1 and
3 should be wired without using layer 2.  Layer 3 (or layer 1 if
layer 3 channels are not available) is used for 2-channel jogs in
layer 2 to free as many channels as possible in layer 1 for
horizontal wiring segments. This avoids vias from layer 1 to layer 3,
which block one channel in layer 2.
C)   3-channel jogs are always wire...