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Electrostatic Discharge Protection for Mixed Voltage Interface

IP.com Disclosure Number: IPCOM000121510D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Au, WM: AUTHOR

Abstract

An electrostatic discharge (ESD) protection network is shown for I/O circuits with mixed voltage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Electrostatic Discharge Protection for Mixed Voltage Interface

      An electrostatic discharge (ESD) protection network is
shown for I/O circuits with mixed voltage.

      ESD protection utilizing the dual rail diode approach is well
known. Typically, PN junction diodes are employed in the design (Fig.
1), and both diodes are not conducting. Under ESD transient
conditions, one of the diodes is forward biased and dissipating
energy either to ground or to the Vdd node, depending on the ESD
polarity.  The structure is useful only when the maximum I/O voltage
is not greater than the supply voltage, or a conduction current will
occur.  Therefore, the structure is not applicable to I/O circuitry
where a mixed voltage interface is required, e.g., Vdd = 3.6V, Vin =
5V.

      Referring to Fig. 2a, one way to make use of the dual rail
diode approach for a mixed voltage interface is to add more diodes to
sustain the voltage drop Vin - Vdd. However, the total gain of the
equivalent PNP circuit (Fig. 2b) causes an unacceptable forward
leakage current from Vin to Vdd. Adding more diodes does not solve
the transistor gain problem. Also, this approach is not practical due
to an increase in silicon area.

      The new ESD protection circuit shown in Fig. 3 will circumvent
the aforementioned problems. It consists of a PN junction diode (D1)
and Schottky diodes (D2, ..., Dn). The number of Schottky diodes
required (N = 5 or 6, typically) depends on Vin, Vdd, and forward
...