Latched I/O AC Test Using a Reduced Pin Boundary Scan Logic Test Method
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
An AC interconnect test method for logic and array chips is shown for multiple chip modules (MCMs) which utilize level sensitive scan design (LSSD) shift register latches (SRLs).
Latched I/O AC Test Using a Reduced Pin Boundary Scan
interconnect test method for logic and array chips
is shown for multiple chip modules (MCMs) which utilize level
sensitive scan design (LSSD) shift register latches (SRLs).
I/Os on multiple chip modules are AC tested by
contacting the I/O pads with AC test lines. By adding an XOR logic
circuit in the LSSD SRL test path, an AC latched I/O test can be
performed with existing external I/O deterministic stuck-fault
patterns with no more simultaneous switch noise than encountered with
a DC test.
Fig. 1, an XOR logic circuit is added to the test
path between the SRL boundary scan register and the off-chip driver
(OCD). One leg of the two-way input is used as a data inverter. By
combining an OCD and off-chip receiver (OCR) in each MCM latched I/O
cell of a logic or array chip, an AC "round trip" test can be made
from a boundary scan string on each chip without contacting the I/O
pad with AC test lines. Note that the data inhibit line is used to
ripple all OCDs on and off after a scan string load cycle to avoid
orthoganality (contention) between MCM chips during scan load/unload.
Also, the OCD/OCR AC frequency is independently controlled by
switching a single XOR (invert data) primary unlatched-input
independent of the SRL string AC timing frequency. Further, this
method uncouples AC Idd noise from internal chip logic simultaneous
switch Idd. The int...