Browse Prior Art Database

Device Test Method Using Power Supply Current Signature Comparison

IP.com Disclosure Number: IPCOM000121524D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Takahashi, Y: AUTHOR [+2]

Abstract

Disclosed is a method for testing logic devices by comparing device power supply current signatures with known signatures measured with good devices. Threshold levels for determination of pass/fail are set to reflect device unique offset voltage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Device Test Method Using Power Supply Current Signature Comparison

      Disclosed is a method for testing logic devices by
comparing device power supply current signatures with known
signatures measured with good devices.  Threshold levels for
determination of pass/fail are set to reflect device unique offset
voltage.

      Fig. 1 shows the outline of this invention.  Memory M1 stores
typical IDD (power supply current) values measured with known good
devices for each of the test patterns.  The values are sampled when
DUT (device under test) is at a stable state after switching in
response to the application of the test pattern.  The value consists
of DUT unique offset and logic unique supply current (IDD signature).

      IDD signature from the DUT measured with a selected test
pattern is compared with the corresponding value in M1. If the
difference exceeds a predetermined limit, the DUT is judged "BAD".
This method enables to compensate for process variations by
subtracting the offset value and provides accurate IDD test.  The
memory M1 may be an unused channel and vector buffer of a LSI tester.

      Fig. 2 shows an example of this test method implemented with a
LSI tester.  The steps of this method are:
(1) Beforehand, IDD values measured with good devices are digitized
and stored in the pattern buffer of the LSI tester.
(2) Test pattern(s) selected for a DUT of a given lot are applied to
the DUT.  The digitized IDD value for the test pattern...