Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Direct Memory Redundancy

IP.com Disclosure Number: IPCOM000121531D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Montoye, RK: AUTHOR [+4]

Abstract

Disclosed is a technique to implement redundancy with no performance degradation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Direct Memory Redundancy

      Disclosed is a technique to implement redundancy with no
performance degradation.

      The conventional technique to implement redundancy is to use
peripheral circuitry (1) to detect defects, (2) to suppress incoming
word line signals that feed the array, and (3) to invoke redundancy
circuitry to access the array.  The result is lower performance.  An
extra delay to detect whether redundancy has been invoked must be
added to the normal access, no matter whether redundancy is used or
not. This delay can be very significant and is a critical factor for
the designer to decide whether or not to incorporate redundancy.

      The Direct-Memory Redundancy (DMR) technique in this disclosure
solves the above performance problem.  Like DMA, DMR does not
interfere with the normal access data flow (CPU for DMA), but
accesses memory directly without any interference from the peripheral
circuitry.  The normal path and redundancy path are accessed in
parallel.  The decision to select which path is made at the array
level; hence, no time is lost due to redundancy circuitry
interrogation.

      Fig. 1 shows the conventional way of implementing redundancy.
The redundancy decoder and circuitry must be checked first before the
regular decoder.  If the redundancy decoder is activated, this means
that the redundancy cell is selected.  The regular decoder and the
defected cell must be deactivated by a signal from redundancy.  This
introduces a delay into the access path, hence lower performance.

      Fig. 2 shows the DMR technique of this disclosure.  The
redundant and regular decoders are accessed in parallel. Both word
lines drive the array.  Note that in the conventional way, there is
one and only one word li...