Browse Prior Art Database

Programmable Bus Interface Unit for Personal Computers

IP.com Disclosure Number: IPCOM000121549D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Huynh, DQ: AUTHOR

Abstract

Described is a programmable bus interface unit (BIU) for personal computers equipped with Micro Channel* architecture (MCA). Both static and dynamic methods of a programmable BIU are described so that a processor complex local bus can support MCA bus systems for use with processors which operate at different clock speeds.

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Programmable Bus Interface Unit for Personal Computers

      Described is a programmable bus interface unit (BIU) for
personal computers equipped with Micro Channel* architecture (MCA).
Both static and dynamic methods of a programmable BIU are described
so that a processor complex local bus can support MCA bus systems for
use with processors which operate at different clock speeds.

      The programmable BIU is a state machine based on the processor
input clock of the microprocessor, since it is the fastest clock in
the system.  The clock allows sampling of asynchronous signals from
the MCA channel and makes possible the generation of control signals
to the channel at a fine resolution.

      In MCA bus systems, the processor complex local bus interfaces
to the MCA bus through a BIU implemented with either various discrete
logics or very large system integration (VLSI) circuits.  Typically,
the processor complex local bus timing specifications vary when
processors run at different frequencies.  In the prior art, the BIU
was often redesigned to accommodate changes in timing requirements.
The concept described herein provides a means whereby the BIU is made
to be programmable over a wide range of frequencies so as to
accommodate changes in the timing requirements of the processors.

      Generally, the control signals generated to the MCA bus by the
BIU which are of interest consist of the following groups:
          -SBE[3:0]
          -SBHE, ULA0, AI
          -SMEM/IO, -S0, -S1
          -ADL, -CMD, -FCMD
          -XLT

      The focus of the concept is on (S0 & S1), -ADL, and especially
-CMD (-FCMD is similar).  The generation of the above control signals
is based on the same mechanism.  The processor's input clock is used
as the time unit, and the beginning of the processor cycle is used as
the reference. The start and stop times which define the active
interval of each of the control signals can be determined for a given
frequency in order to comply with required timing specifications.

      The programmable BIU is designed so that it can generate the
required control signals with the correct timings to the channel bus
based on the start and stop time information associated with each
signal for a given frequency.  Fig. 1 shows a functional block
diagram for the generation of a control signal.  Master counter 10 is
enabled at the beginning of each local entry programmable bus-2
(LEPB-2) cycle by means of start cycle 11.  For each clock
transition, the counter 10 output is compared in comparator 13
against the start value for a given control signal stored in module
12.  This stored value can be either loaded dynamically or loaded
from a lookup table.  If a true comparison is made, the signal is
made active through adder 14.  The same approach is made again using
the stop value from stop module 15 so as to deac...