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Browse Prior Art Database

Linear To Physical Memory Mapping by Bus Masters in Virtual Memory Systems

IP.com Disclosure Number: IPCOM000121552D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 133K

Publishing Venue

IBM

Related People

Gohda, Y: AUTHOR [+4]

Abstract

Described is a facility for virtual memory computer systems that provides linear-to-physical memory mapping by a bus master. The facility enables a bus master moving large amounts of data to operate within the paging environment of protect mode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Linear To Physical Memory Mapping by Bus Masters in Virtual Memory
Systems

      Described is a facility for virtual memory computer
systems that provides linear-to-physical memory mapping by a bus
master.  The facility enables a bus master moving large amounts of
data to operate within the paging environment of protect mode.

      Typically, processors of a computing system have integrated
management units (MMUs) that allow for increased memory addressing
and a virtual memory based on segmentation and paging.  The MMUs are
in tegrated to enable the processors to quickly evaluate virtual
addresses and to map them into the corresponding physical address.
Processors, operating in protect mode, divide programs into uniformly
sized pages which bear no direct relationship to the logical
organization of the programs, although the programs still retain
linear contiguous views of the memory.  Bus masters which provide
addresses directly to memory without intervention from the processor
must work within the system's paging environment without the benefit
of the main processor's MMU.  Problems can occur in the transferring
of physical address information to a bus master controller when data
is transferred to/ from system memory operating in virtual mode.

      One solution to the problem outlined above is for each bus
master to duplicate the MMU logic of the main processor in its own
design.  However, a large amount of circuitry would be required to
implement even a subset of the MMU function, since a translation
lookaside buffer (TLB) is required to maintain adequate performance.
Since memory uses a large portion of available area in a very large
scale integration (VLSI) implementation, adding TLB and additional
MMU logic necessitates a trade-off function or an increase in the
size of the circuit chip.  In addition, the speed required to access
the TLB may force it to be implemented using discrete devices rather
than available memory macros. The access time necessary for
translation may not only require the TLB to be implemented in
discrete devices, but may also force the designer to use a faster
technology than is needed for the rest of the bus master functions.

      Another disadvantage to each bus master having an MMU is the
difficulty in maintaining coherency as the main processor exchanges
unpinned pages in and out of memory. Each TLB must reflect the
current state of the page table at all times.  For bus masters moving
large quantities of data and the need for assistance in crossing page
boundaries, it is desirable to provide a simple mechanism to allow
the bus masters to operate in the system's paging environment without
the need for duplicating the MMU operation of the main processor.

      The concept described herein provides a simple method which
allows a bus master moving large amounts of data to operate within
the paging environment of protect mode. Software is required to
maintain a table of consecutively...