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High Speed BiCMOS Charge Pump

IP.com Disclosure Number: IPCOM000121554D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 110K

Publishing Venue

IBM

Related People

Soyuer, M: AUTHOR

Abstract

Disclosed is a high-speed BiCMOS charge pump circuit capable of operating with zero steady-state phase error in high-speed phase-locked loop applications. Because of the isolation between the charge pump and the loop filter during the open-circuit (null) state, the phase error is limited by the leakage currents rather than the circuit mismatches.

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High Speed BiCMOS Charge Pump

      Disclosed is a high-speed BiCMOS charge pump circuit
capable of operating with zero steady-state phase error in high-speed
phase-locked loop applications.  Because of the isolation between the
charge pump and the loop filter during the open-circuit (null) state,
the phase error is limited by the leakage currents rather than the
circuit mismatches.

      A current charge pump is commonly used to convert the voltage
pulses from the phase detector to current pulses which drive the loop
filter in a phase-locked loop.  The charge pump delivers a current of
+I or -I to the loop filter whenever the phase detector logic state
is UP or DOWN, respectively.  The most significant property of charge
pump, however, is its behavior when there are no pulses from the
phase detector.  Ideally, in this third state, the charge pump should
be isolated from the loop filter, enabling a zero static phase error
at steady state.  This open-circuit state is not encountered in the
conventional continuous-time phase-locked loops.

      High-speed charge pumps usually employ bipolar technology for
faster switching.  However, due to the difficulty of obtaining high-
speed complementary current sources in bipolar technology, a
compromised solution is commonly adopted.  Fig. 1 shows a possible
implementation of this approach.  Note that the PNP current source on
top (IPNP) is not switched at all.  All the switching is done by the
lower NPN differential pairs.  This way a current of either zero or
2INPN is subtracted from IPNP .  Therefore, the filter capacitor is
either charged by IPNP or discharged by INPN assuming matched current
sources.  When there are no UP or DOWN pulses from the phase detector
(i.e., both low), no current should flow through the filter
capacitor.  The problem is that these current sources are never
perfectly matched and the ideal null (open circuit) condition is
never realized.  Therefore, the static phase error is still
determined by the circuit mismatches, as in the case of conventional
phase-locked loops, instead of second-order effects such as the
leakage currents which would result in much smaller (ideally zero)
phase errors.  Obviously, a high-speed complementary bipolar process
will provide an immediate solution to this problem.  However, as will
be described in the next section, a novel circuit design with a
BiCMOS process can eliminate the need for fast PNP current sources
and still...