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CMOS Set Reset Flip-flop with Set Dominant

IP.com Disclosure Number: IPCOM000121560D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR

Abstract

A set dominant flip-flop is a well-known logic element. Conventional implementation such as shown in Fig. (a) requires 10 FET devices. The disclosed latch of Fig. (b) requires only 6 FET devices with 4 devices for the basic flip-flop plus 2 NFETs controlled by the SET and RESET signals. The same functionality is performed, but the result is better density and better performance.

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CMOS Set Reset Flip-flop with Set Dominant

      A set dominant flip-flop is a well-known logic element.
Conventional implementation such as shown in Fig. (a) requires 10 FET
devices.  The disclosed latch of Fig. (b) requires only 6 FET devices
with 4 devices for the basic flip-flop plus 2 NFETs controlled by the
SET and RESET signals. The same functionality is performed, but the
result is better density and better performance.

      A Set/Reset latch is usually made with two 2-input NOR gates
with each output (True or Complement) connected to one of the inputs
of each NOR gate.

      The operation is summarized as follows:
    Set   Reset   Qt+1
     0     0      Qt  Store data
     0     1      0   Reset at 0
     1     1      1   Set at 1
     1     1      1   Set dominant

      As in a SRAM memory cell, a symmetrical action on both nodes of
the flip-flop is done during the writing.
     When SR=00, NFETs N3 and N4 are off, the data is maintained in
the latch.
     When SR=01, NFET N3 is on, and thus the output goes to O.
     When SR=10, NFET N2 is on, and thus the output goes to 1.
     When SR=11, NFETs N2 and N3 are on with the output going to 1.

      It can be noticed that always the True and Complement outputs
are opposite. This is not the case with the circuit of Fig. (a) if
only NOR gate outputs are considered.