Browse Prior Art Database

Microprocessor-based System to Control or Monitor Packet Transfers

IP.com Disclosure Number: IPCOM000121576D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes an interrupt control mechanism which provides the means for a microprocessor to monitor and control the routing of packets, detect errors and allow the programmer the flexibility to sense the status of each packet transfer or to have certain bits cause interrupts by setting the mask on for each bit individually.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Microprocessor-based System to Control or Monitor Packet Transfers

      This article describes an interrupt control mechanism
which provides the means for a microprocessor to monitor and control
the routing of packets, detect errors and allow the programmer the
flexibility to sense the status of each packet transfer or to have
certain bits cause interrupts by setting the mask on for each bit
individually.

      The interrupt/status bits defined for each input data buffer
(pockets being received) consists of three interrupt bits.  These
interrupt/status bits along with their associated mask bits may be
sensed by the microprocessor at any time so that the status of
packets being received may be determined by the microprocessor.

      Each input data buffer has the following interrupt/status bits.
      1.   FULL - This indicates that a packet has been
           completely transmitted to the data buffer or it
           will be set when Burst Return drops (goes
           inactive).
      2.   EXPEDITE -  The expedite bit is set when the
           expedite command bit in word 1 of data transfers
           is active.
      3.   BUSY/ERROR - This bit is first set when an address
           compare of the packet destination and the adapter
           device address is made when the first Packet
           Service signal is active immediately following a
           Burst Return.  This bit will remain set until the
           Full bit is set.  It will then be reset if no
           error has occurred or it will remain set to
           indicate an error condition in the data buffer.

      The two input command buffers have only one interrupt/status
bit that is set when each buffer is filled. Similarly, the two
overflow buffers have only one full bit for each buffer and when set
indicates that an overflow condition has occurred.

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