Browse Prior Art Database

Emitter Dotting BiCMOS Circuit

IP.com Disclosure Number: IPCOM000121579D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR

Abstract

Described is an emitter dotting bipolar CMOS (BiCMOS) circuit designed to improve functionality and performance. The circuit uses BiCMOS gates with an open emitter output stage to allow emitter dotting. This enables many important logic functions to be implemented with less logic levels.

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Emitter Dotting BiCMOS Circuit

      Described is an emitter dotting bipolar CMOS (BiCMOS)
circuit designed to improve functionality and performance. The
circuit uses BiCMOS gates with an open emitter output stage to allow
emitter dotting.  This enables many important logic functions to be
implemented with less logic levels.

      A typical CMOS or conventional BiCMOS gate implementation for a
32-bit comparator is shown in Fig. 1. A maximum fan-in of three is
assumed because the CMOS gate and the BiCMOS gate become quite slow
for a large fan-in due to the serial devices used.  There are five
logic levels required for this implementation.

      Fig. 2 shows the BiCMOS XOR gate.  The key difference between
the circuit of Fig. 2 and the circuit of Fig. 1 is that the output
stage has an open emitter.

      Fig. 3 shows an implementation of a 32-bit comparator with this
XOR gate.  The emitters of the pull-up bipolar output devices of the
32-bit XOR gated are tied together to a load device.  In this case, a
resistive load is used but other load devices may be used as well.
The delay of the BiCMOS 32-bit comparator has only one logic gate
delay. Therefore, the circuit can significantly be faster than that
of the conventional implementation of Fig. 1.