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DC-DC Convertor Self Synchronization Circuit

IP.com Disclosure Number: IPCOM000121580D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 5 page(s) / 215K

Publishing Venue

IBM

Related People

Brandl, TA: AUTHOR

Abstract

Described is a self-synchronization circuit for parallel DC-DC convertors and is designed for use in fault-tolerant computers where master clock architecture is not tolerated. A basic design is described along with an alternative circuit design and changes to the circuit to ensure reliable operation.

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DC-DC Convertor Self Synchronization Circuit

      Described is a self-synchronization circuit for parallel
DC-DC convertors and is designed for use in fault-tolerant computers
where master clock architecture is not tolerated. A basic design is
described along with an alternative circuit design and changes to the
circuit to ensure reliable operation.

      The self-synchronization circuit requires only one or two
edge-connector pins to accomplish synchronization of multiple DC-DC
convertors.  The backpanel, which distributes DC power input through
edge connectors, contains no active components in accordance with
fault-tolerant restrictions. No radiating synchronization signal line
to the backpanel over long power conductors is required.  The
objective of keeping the switching power sum and difference
frequencies off of the DC power input cable is achieved with the
synchronization method.

      Generally, power supply regulator integrated circuits operate
with a resistor-capacitor (RC) controlled oscillator.  Usually for a
bank of parallel regulators, the oscillators of each regulator are
designed for the same frequency.  If synchronization is desired, a
master clock signal is usually provided from an external source.
However, utilizing the master clock signals is generally considered
contrary to master/slave fault-tolerant computer operation, unless a
master module is automatically designated.

      The concept described herein provides for master designation by
virtue of the highest oscillator frequency. Each of N modules will
have its own oscillator, and due to component tolerances and other
factors there will be a tolerance on the nominal frequency that each
module is set at.  Only one will be the fastest and therefore will
have the shortest period.  As a result, the circuit is built around a
synchronization bus common to all modules which will re-align the
slower oscillators to match the fastest oscillators.  In this way,
there are no special construction or components required to be built
into any of the modules to force one of the modules to be the master.

      The basic self-synchronization principle relies on the natural
deviations that occur about the nominal frequency for a master to
take control.  Fig. 1 shows the basic functioning components of a
self-synchronization module. Omitted are all but the logic components
necessary for understanding how the synchronization principle
operates. Each module performs an on-card DC-DC conversion and each
module is identical and can be plugged into an identical printed
circuit card edge connector supplying bulk DC power through a passive
backpanel.

      It is assumed that the oscillator local to pulse width
modulation (PWM) unit U1 is the fastest among a bank of identical
parallel convertors all connected in the same manner to both the sync
bus and a bulk DC input (not shown). PWM unit U1 is a current-mode
control integrated circuit with the three pins 4...