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Browse Prior Art Database

Increased Surface Area Capacitor by Laser Interference

IP.com Disclosure Number: IPCOM000121583D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Hodgson, RT: AUTHOR [+2]

Abstract

Disclosed is a method to increase capacitor surface area in an advanced DRAM with stacked capacitor cells. The capacitor is formed from an insulator (SiO2) between two polysilicon layers. One way to increase the surface area is to corrugate the polysilicon surface in a controlled way. A fabrication technique, based on laser interfero metry is proposed here to achieve this goal. The blanket polysilicon layer 1 that serves as the bottom (node) capacitor plate is covered with photoresist 2. Either the polysilicon surface 3 is first planarized, or the photoresist 2 should be planarized. Laser interference using two coherent laser beams 4 and 5 is then used to create a corrugation pattern 6 in the resist, as shown in Fig. 1. This exposure can be repeated in two directions to create an X-Y grid of intersecting lines.

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Increased Surface Area Capacitor by Laser Interference

      Disclosed is a method to increase capacitor surface area
in an advanced DRAM with stacked capacitor cells.  The capacitor is
formed from an insulator (SiO2) between two polysilicon layers.  One
way to increase the surface area is to corrugate the polysilicon
surface in a controlled way.  A fabrication technique, based on laser
interfero metry is proposed here to achieve this goal.  The blanket
polysilicon layer 1 that serves as the bottom (node) capacitor plate
is covered with photoresist 2.  Either the polysilicon surface 3 is
first planarized, or the photoresist 2 should be planarized.  Laser
interference using two coherent laser beams 4 and 5 is then used to
create a corrugation pattern 6 in the resist, as shown in Fig. 1.
This exposure can be repeated in two directions to create an X-Y grid
of intersecting lines.

      An entire chip site or an entire wafer can be exposed at the
same time without lining up the features with the underlying device
features.  If we use a 321.5 nm He-Cd laser with the first light
impinging on the surface at grazing incidence, we can expect the peak
to peak distance in the exposed and developed photoresist to be about
170 nm. For a device "footprint" of .7 by .7 micron, we expect to
make 4 fins by reactive ion etching (RIE) of the poly through the
holes in the photoresist.  If the aspect ratio of the 4 fins is 10,
the area of the resulting insulator oxide 7 between...