Browse Prior Art Database

Converter Circuit

IP.com Disclosure Number: IPCOM000121587D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Chao, H: AUTHOR [+2]

Abstract

Disclosed is a delay-free converter circuit that couples bipolar logic gates and CMOS logic gates operating at different logic levels and power supplies.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Converter Circuit

      Disclosed is a delay-free converter circuit that couples
bipolar logic gates and CMOS logic gates operating at different logic
levels and power supplies.

      As devices are scaled to smaller dimensions, the power supply
of CMOS circuits scales with device dimensions; however, the supply
voltage of scaled bipolar circuits remains constant.  In addition,
the logic swing of the CMOS device is equal to the power supply
voltage, while that of the bipolar devices is only a fraction of the
supply voltage.  The speed potential of a BiCMOS technology is fully
exploited if the circuits are: (1) implemented with clusters of
bipolar macros and CMOS macros, and (2) operated with optimized,
possibly different, power supplies.  This circuit configuration
requires delay-free converter circuits that shift the logic level
between the macros.

      Fig. 1 shows the delay-free converter circuit.  In this
illustration, the bipolar power supply is 3.6 V and the CMOS supply
is 2.5 V.  The second stage is an ECL-CMOS converter, called ECL
logic/shifter.  It not only boosts up the signal to the CMOS level
but also performs logic functions (OR,NOR).  Its input signal level
is one diode drop from the standard ECL output, which can be realized
without delay penalty.  From the system point of view, the converter
does not introduce gate delay, since the converter performs a logic
function.  As shown, the first stage is a standard bipolar ECL gate
with an...