Browse Prior Art Database

Shared and Exclusive Locking

IP.com Disclosure Number: IPCOM000121589D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

King, RP: AUTHOR

Abstract

Disclosed is a method for the efficient maintenance of a lock offering shared and exclusive modes. Different processors in a multiprocessor can acquire and release the lock in shared mode without disturbing each other's private cache memories.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Shared and Exclusive Locking

      Disclosed is a method for the efficient maintenance of a
lock offering shared and exclusive modes.  Different processors in a
multiprocessor can acquire and release the lock in shared mode
without disturbing each other's private cache memories.

      The data structure representing the lock is a set of N spin
latches, numbered from 1 to N.  (N is the number of users which will
be trying to use this lock.  These users might be processors in a
multiprocessor or processes in a multiprogramming system.)  In order
for user i to acquire a lock in shared mode, it acquires the spin
latch numbered i. To release a shared mode lock, release latch
numbered i.  A lock is acquired in exclusive mode by acquiring all of
the spin latches, in numerical order, from 1 to N.  One releases the
exclusive lock by releasing all of the spin latches.

      The N spin latches can each be placed in a different cache line
from the others.  This could be done, for example, by declaring the
spin latches as elements in an array indexed from 1 to N*LS, where LS
is the number of spin latches that fit in a cache line, making sure
that the array is placed on a cache line boundary.  This provides LS
locks, numbered 1 to LS.  Processor i uses array element 1+i*LS-x as
its spin latch to acquire lock x in shared mode.  Since the array
starts on a cache line boundary, the latches 1 to LS are all in one
cache line, latches LS+1 to 2*LS on the next, and so on...