Browse Prior Art Database

Reducing Interrupt Latency in Multi-tasking Operating Systems Running On PC and PC Compatibles/ Clones

IP.com Disclosure Number: IPCOM000121592D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Kogan, MS: AUTHOR

Abstract

This article describes a method for use in a personal computer (PC) for operating system (OS) interrupt handling and programming the Intel 8259 programmable interrupt controller (PIC) to reduce interrupt latency to a fixed-rate minimum for each interrupt level.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reducing Interrupt Latency in Multi-tasking Operating Systems Running
On PC and PC Compatibles/ Clones

      This article describes a method for use in a personal
computer (PC) for operating system (OS) interrupt handling and
programming the Intel 8259 programmable interrupt controller (PIC) to
reduce interrupt latency to a fixed-rate minimum for each interrupt
level.

      Some PC architectures utilize two 8259 PICs in cascaded
formation so as to provide the main CPU with interrupts from a
variety of sources.  The PIC is capable of prioritizing interrupts
from multiple sources and completing the interrupt acknowledge cycle
to interrupt the main CPU so that it may service an interrupting
device [*].  In these PC architectures, the "slave" 8259 is cascaded
onto interrupt request (IRQ)2 of the "master" 8259.

      A 16-bit OS programs the 8259s in a mode called fully nested
mode (FNM).  In FNM, the interrupt requests are ordered in priority
from 0 to 7 (highest).  When an interrupt occurs in FNM whether on
the master or slave, the 8259 selects the highest priority IRQ and
places its vector on the bus.  Additionally, the bit for the selected
level in any interrupt service register (ISR) is set.  This bit
remains on until the interrupt service routine on the main CPU issues
an end of interrupt (EOI) command.  While the bit in the ISR is set,
all further interrupts for the same level or lower priority level are
inhibited, while higher priority level IRQs continue to generate
IRQs.

      The above interrupt sequence is exactly the situation in the
16-bit OS, with the qualification that the interrupt level priorities
have been rotated so that IRQ3 is the highest level.  This is to
allow the asynchronous devices which use IRQ3 and IRQ4 to be the
highest priority.  The problem that exists in this situation is that
relatively low priority device's interrupt handling will be postponed
until the higher priority device(s) issue(s) an EOI command in its
own device specific interrupt handler.

      When an interrupt is delivered to the main CPU from the 8259
PIC, the 16-bit OS first-level interrupt handler (FLIH) gets control.
It then begins dispatching the interrupt to device specific
second-level i...