Browse Prior Art Database

Extending Battery Back-up Time of Memory Arrays

IP.com Disclosure Number: IPCOM000121596D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Cody, WR: AUTHOR [+3]

Abstract

Disclosed is a technique for extending the data retention time of battery backed-up memory circuits.

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Extending Battery Back-up Time of Memory Arrays

      Disclosed is a technique for extending the data retention
time of battery backed-up memory circuits.

      In large computers, power supply voltages are often adjustable
to allow the operating margins of system logic to be tested.  "These
computers also typically employ a sophisticated power controller
system to turn power supplies on and off, monitor fault detectors,
and adjust the power supplies during margin testing." [*].

      When AC mains power fails, and batteries are to be the source
of power, the power controller places the computer in standby mode to
minimize battery drain.  During standby, unused functions are powered
off and memory is placed in a "keep-alive" mode.  Additional power
may be saved by utilizing the adjustability of the power supplies to
reduce memory supply voltage to a minimum.  A battery support time
extension of 20% or more may be achieved using this technique.

      Reference
(*)  R. Pease, "Programmable Power Regulators Help Check Out Computer
System Operating Margins," National Semiconductor Linear Brief, 49 .