Browse Prior Art Database

Digital Data Rate Detector for Computer Systems

IP.com Disclosure Number: IPCOM000121605D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 138K

Publishing Venue

IBM

Related People

Holsteen Jr, JF: AUTHOR

Abstract

Described is a digital data rate detector circuit for computer systems which utilize flexible attachment media, such as tape or diskette drives. The detector circuit is designed to detect the correct data rate by actually timing the data pulses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Digital Data Rate Detector for Computer Systems

      Described is a digital data rate detector circuit for
computer systems which utilize flexible attachment media, such as
tape or diskette drives.  The detector circuit is designed to detect
the correct data rate by actually timing the data pulses.

      Since media drive units used in computer systems operate at
many different recording speeds, methods commonly used in determining
the data rate have relied on read circuit phase-locked loop
synchronization techniques.  However, recording frequency variations
have resulted in improper detection, thereby rendering a portion or
the entire media unreadable.

      In the case of diskette drives, in prior art, the lowest read
oscillator was selected and a read command issued to determine if any
identification (ID) record could be read within one revolution.  If
no ID was read, during the next revolution a read attempt would be at
the next higher data rate.  This routine typically began with a 250
Kbps data rate, followed by 300 Kbps, 500 Kbps, etc.  Any time an ID
was read, the read oscillator was locked at that frequency until
another diskette change occurred.  Difficulty could be experienced in
distinguishing 250 Kbps and 300 Kbps data rates due to their minimum
frequency spread.  With systems which use an analog phase-locked loop
data separator, the bandwidth must be sufficiently wide to lock and
track the data stream.  This could present problems when attempting
to lock-on to a 300 Kbps data rate, since it may have locked-on as a
250 Kbps rate, thereby resulting in the systems inability to read the
diskette.  To overcome this problem and to accommodate the ability to
read several different data rates, computer systems have been known
to have used multi-speed drives.

      Other problems have occurred in prior art techniques, such as
when write signal discontinuities at the beginning and/or the end of
the data field pulls the phase-locked loop oscillator to an
unrecoverable frequency condition, commonly referred to as harmonic
lock.  This condition could prevent the track from ever being read
again.  As faster data rates are developed for the flexible media,
the determination of the frequency of the magnetically recorded
information requires that the proper oscillator be selected to drive
the read circuits.

      The concept described herein provides a data rate detector
circuit to determine the correct data rate by actually timing the
data pulses.  The circuit eliminates the possibility of having an
incorrect decision, or the need for additional mechanical switches.
The detector does not rely on any drive ID line but is dependent only
on the frequency of the recorded information.  The data rates will
always be detected correctly by the detector circuitry.  It is used
only for data rate detection and has no effect on the rest of the
data separator circuitry, regardless of the type used....