Browse Prior Art Database

Multiple Bus Masters with Arbitration and Preempt Capability For Personal Computers

IP.com Disclosure Number: IPCOM000121609D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+3]

Abstract

Described is a technique to provide multiple bus masters with arbitration and preempt capability for personal computers (PCs) with the advanced technology (AT) style bus. Multiple bus master adapters share the bus with preemption so as to allow an unmodified PC AT* style bus to duplicate certain features of MICRO CHANNEL* architecture.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple Bus Masters with Arbitration and Preempt Capability For
Personal Computers

      Described is a technique to provide multiple bus masters
with arbitration and preempt capability for personal computers (PCs)
with the advanced technology (AT) style bus. Multiple bus master
adapters share the bus with preemption so as to allow an unmodified
PC AT* style bus to duplicate certain features of MICRO CHANNEL*
architecture.

      Typically, multiple bus masters can share the Micro Channel bus
in an architected fashion with provisions for preemption and a
maximum time limit on the bus.  Preemption allows a device to
indicate a need for the bus and to encourage the current owner of the
bus to release control. The maximum time limit constraint ensures
that no adapter will hold onto the bus so long that memory refresh is
delayed with the attendant system integrity problems that it causes.
If memory refresh is delayed too long, the memory will lose data.
Since the AT style bus does not support these features, the concept
described herein provides a means of providing preemption and maximum
time limit capability for an AT style bus without defining any new
signals or affecting existing circuitry.

      Fig. 1 illustrates how an existing AT bus master type of
adapter can gain control of the bus.  This is done by pulling the
data request (DREQ) line corresponding to the assigned direct memory
access (DMA) channel (not shown). The DMA returns a data
acknowledgement (DACK) for that channel.  If control of the bus is
required, the master activates the -MASTER line as depicted in Fig.
1.  The bus master adapter releases the bus by deactivating both the
-MASTER signal and its DREQ signal.

      For those devices that cannot transfer data themselves, either
the processor or the DMA controller (not shown) is required to do the
actual data move.  Devices, such as the PC network card and the
diskette, do not move the data themselves but instead use the
DREQ/DACK interface to request the DMA controller to move the data.
The DMA controller must be programmed ahead of time with the address
and the byte count so as to provide the address to transfer to or
from and the total number of bytes to be moved.  The DMA controller
monitors the DREQ signal lines. ...