Browse Prior Art Database

Semicustom CMOS Timing Chain

IP.com Disclosure Number: IPCOM000121648D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Clemen, R: AUTHOR [+2]

Abstract

This article describes a semicustom layout technique which allows the design of highly structured embedded memory arrays. By using a minimum set of predefined basic device elements, the entire timing chain circuitry can be composed easily and quickly without sacrificing circuit performance. Thus, the gap between memory and logic design cycle times is reduced.

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Semicustom CMOS Timing Chain

      This article describes a semicustom layout  technique
which allows  the  design  of  highly  structured  embedded memory
arrays.  By using a minimum set of predefined  basic  device
elements,  the entire timing chain circuitry can be composed easily
and quickly without sacrificing circuit  performance. Thus, the gap
between memory and logic design cycle times is reduced.

      Normally,  high-speed  static  CMOS RAMs are internally
clocked, i.e., the signal propagation through  the  critical path  is
controlled and timed by a sequence of clock phases. To  ensure
reliable  circuit  functions  and  to  meet  the performance
objectives,  the  timing chain circuits must be carefully designed.

      Such  circuits  are  generally designed and laid out in the
same way as the pitch  matching  circuits  of  the  data path;   they
are  customized,  i.e.,  every  transistor  is tailored individually.
First, the optimum design parameters (FET channel width W and channel
length L) are determined by means of CAD programs.  Then, in the
layout and digitization phase, every  device  is  drawn  separately.
For  maximum circuit  density  in a given layout pitch Y, the
transistors are packed as closely as possible relative to each other.

      This  method  is  particularly  disadvantageous for ASM arrays
embedded on VLSI chips, since it does not  match  the fast  physical
design times of random logic schemes using an automated standard cell
method.  With increasing complexity, the  development  effort  for
customized  circuits  expands rapidly,  if  both  their  performance
and density are to be optimized.    Fine  tuning  a  circuit  in
particular   is cumbersome  and time-consuming, as frequently the
layout has to be reworked if, for example, only a single device size
is to be enlarged.

      A highly structured CMOS layout technique  is  proposed which
preferably uses only two basic transistors to realize the timing and
control ci...