Browse Prior Art Database

Embedded Trace Feature

IP.com Disclosure Number: IPCOM000121650D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Holm, I: AUTHOR [+6]

Abstract

Analyzing hardware problems in the bring-up phase of new chips consumes much time and effort. A clock stop occurring as a result of such problems may take some clock cycles before becoming actually effective. Thus, the contents of the LSSD shift register latches (SRLs) of a state machine or sequencer may change even after a clock stop has occurred. In addition, chip designers are unable to obtain information on the SRL contents prior to such stops. However, a simple standardized interface and some external components allow the designer to look back into the past and check the history, say, the SRL contents, on a clock cycle basis. External off-the-shelf components are easily configurable to any width and depth to suit a random logic group to be tested.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Embedded Trace Feature

      Analyzing hardware problems in the bring-up phase of new
chips consumes much time and effort.  A clock stop occurring as a
result of such problems may take some clock cycles before becoming
actually effective.  Thus, the contents of the LSSD shift register
latches (SRLs) of a state machine or sequencer may change even after
a clock stop has occurred. In addition, chip designers are unable to
obtain information on the SRL contents prior to such stops.  However,
a simple standardized interface and some external components allow
the designer to look back into the past and check the history, say,
the SRL contents, on a clock cycle basis.  External off-the-shelf
components are easily configurable to any width and depth to suit a
random logic group to be tested.

      The random logic to be analyzed is selected and its data routed
to boundary scan SRLs.  In the trace mode, the data is clocked out to
high-speed high-density FIFOs.

      If any clock stop or exceptional condition occurs, the logged
data can be read out and displayed by a service processor (SP) in
response to a read chain command.  Thus, a huge number of data logged
before the occurrence of the stop is readily available for problem
analysis.  Expensive external logging equipment is not required.

      The arrangement used to implement the illustrated embedded
trace feature comprises the following components:
 -    Random logic 1
      Any random logic block (sequencers, state machines, etc.) to be
traced.  The SRL outputs are fed to a central trace multiplexer.
 -    Select SRLs and decoding 2
      A register and decoder for selecting the random logic block.
 -    FIFO interface 3
      3.1  Write clock
           This clock runs continuously to rec...