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Floating Point Approach to A/D Conversion

IP.com Disclosure Number: IPCOM000121653D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 153K

Publishing Venue

IBM

Related People

Hilgendorf, RB: AUTHOR

Abstract

For converting signals of more than 50 dB into eight bits at a sampling rate exceeding 10 MHz, a number of A/D converters are used. All of these converters sample the same source in parallel but with increasing amplification between source and converter. In addition, the converters are capable of detecting an overvoltage or undervoltage at their input. The converter outputs are fed to selection circuitry which selects the output of that converter which is still just within its operating range. The address of the selected converter is encoded and added to the output.

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Floating Point Approach to A/D Conversion

      For converting signals of more than 50 dB into eight bits
at a sampling rate exceeding 10 MHz, a number of A/D converters are
used.  All of these converters sample the same source in parallel but
with increasing amplification between source and converter.  In
addition, the converters are capable of detecting an overvoltage or
undervoltage at their input. The converter outputs are fed to
selection circuitry which selects the output of that converter which
is still just within its operating range.  The address of the
selected converter is encoded and added to the output.

      Circuitry for four A/D converters 1 to 4, connected in parallel
to a chain of four amplifiers 5 to 8 by three delay circuits 9 to
11, is shown in Fig. 1.  The output of each A/D converter is
connected to selection circuitry 12. Reference voltage generation is
not shown, as it depends on the A/D converters being used.

      Selection circuitry 12, illustrated in greater detail in Fig.
2, is substantially A/D converter-independent, which means that parts
of it may be integrated in the converters. The overvoltage and
undervoltage detection circuits are designated as 13 to 15 and 16 to
18, respectively.  There is a set of 6-bit latches 19 to 22, one for
each A/D converter. Latches 23 to 28 are used to store out-of-range
con ditions generated by overvoltage and undervoltage detectors and
applied to them through OR gates 29 to 33.  The output of latches 23
to 28 is fed to PLA (programmable logic array) 34, the output of
which selects the plane of multiplexer 35 to be gated.  The 8-bit
output latch of selection circuitry 12 is designated as 36.  The six
least- significant bits contain the value of the A/D converter
selected, and the two most-significant bits the selection code for
the multiplexer.

      Fig. 3 shows the PLA contents.  Line 37 is the input driven by
latch 23, line 38 the input driven by latch 24, and so on.  The
output, line 43, is connected to the high-order bit of output latch
36, whereas line 44 links the second highest bit of this latch.

      A/D converters 1 to 4 are assumed to be 7-bit wide and adjusted
by the reference voltage such that at -1 V at the input, all output
bits are "0" and at +1 V, all bits are "1".  Each of the amplifiers
5 to 8 has an amplification factor of 10.  For a defined time after
the sampling clock has been rising, the digitized signal is available
at the output of A/D 1.  As A/D's 2 to 4 are fed by the
same clock, their outputs are similar at the same time.   The six
most-signifcant bits of A/D's 1 to 4 are latched into 19, 20, 21 and
22, respectively.  All latch operations are performed in parallel.

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