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Computer Communications High Order Bit Sharing Technique

IP.com Disclosure Number: IPCOM000121655D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 110K

Publishing Venue

IBM

Related People

Keener, DS: AUTHOR [+2]

Abstract

Described is a computer communication logic implementation whereby the number of logic gates is reduced by sharing high-order bits that are common to two separate hardware counters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Computer Communications High Order Bit Sharing Technique

      Described is a computer communication logic
implementation whereby the number of logic gates is reduced by
sharing high-order bits that are common to two separate hardware
counters.

      Typically, the small communications system interface (SCSI)
protocol allows data to be sent from an initiator to a target, or
from a target to an initiator.  A method called "offset" provides a
means of sending data before the target, or the initiator, is ready
to store the data. Therefore, hardware at either end must be
implemented with a first-in-first-out (FIFO), or other temporary
storage register.  Generally, the FIFOs are no more than eight-byte
registers since the SCSI offset rarely exceeds that amount. The
maximum offset supported by the transmission counter is seven bytes
and functions as an initiator or a target.

      The actual data transmission on the SCSI bus is performed with
a request/acknowledge (REQ/ACK) protocol. The target always generates
the REQs, and the initiator always generates the ACKs.  In the case
where the data transfer is from the target to the initiator, the data
is sent on the falling edge of the REQ.  In the case where the data
transfer is from the initiator to the target, the data is sent on the
falling edge of the ACK.  In either case, the number of REQs that
have been sent can be larger than the number of ACKs that have been
sent, by the offset value. Fig.  1 shows the typical REQ/ACK protocol
timing.  The target must control the offset by ensuring that it does
not go over the allowed amount.  This is usually from one to seven
bytes and is dependent on the application.

      The data transfer byte counter is typically a 24-bit counter
which allows for transfers of up to 16 MBytes.  The byte counter
counts the bytes as they are transferred into the gate array.  The
logic and state machines that control the data transfer are designed
to operate until the byte counter reaches zero.  Problems can occur
when the counter acts as a target receiving data from the SCSI.  In
this case, the counter can send REQs out on the bus before the data
is sent by the initiator.  It can send out as many as seven
outstanding REQs before receiving the data for the first REQ.  This
can be a problem if the state machine controlling the generation of
the REQs stays active until the byte count reaches zero.  At the...