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Hardware Managed Interrupt Status Queue and Manual Vector Generator For Multiple Channel Communications Controller

IP.com Disclosure Number: IPCOM000121657D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 7 page(s) / 293K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+4]

Abstract

An entity used for the collection, queuing and prioritization of interrupts from 32 full duplex communications channels is described. Also described is a method of encoding a total of 67 unique interrupt types and presenting them on a processor bus to allow for direct vectoring to an associated interrupt handler, a technique referred to here as Manual Vectoring.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 28% of the total text.

Hardware Managed Interrupt Status Queue and Manual Vector Generator
For Multiple Channel Communications Controller

      An entity used for the collection, queuing and
prioritization of interrupts from 32 full duplex communications
channels is described.  Also described is a method of encoding a
total of 67 unique interrupt types and presenting them on a processor
bus to allow for direct vectoring to an associated interrupt handler,
a technique referred to here as Manual Vectoring.

      Fig. 1 illustrates the described entity (INT) and the
environment in which it is utilized.

      The INT device resides within a very large-scale integrated
(VLSI) chip that is used to perform data link control and direct
memory access (DMA) functions for an integrated service digital
network (ISDN) primary rate network.  This network essentially allows
for 32 full-duplex communications channels to operate independently
over a common physical interface.

      INT therefore receives interrupt indications for each of the 32
channels.  Because of the multiplexing nature of the ISDN connection,
only one channel will be active at a time, thereby preventing more
than one channelized interrupt source from activating at the INT
interface at any given time.  Each channel can provide two distinct
types of interrupts: End of Process (EOP) and Channelized Error (CE).

      EOP interrupts are generated when a normal operation associated
with the communications channel has completed, such as an end of
frame indication being received or the exhaustion of a DMA buffer
space having occurred.  Fig. 2 shows the EOP Interrupt Status Word
(EOPISW).  When INT detects a channel EOP interrupt, it will capture
associated status and store the information (EOPISW) in a queue which
is designated specifically for that channel. Since each channel can
queue up to sixteen interrupt status words, INT also increments the
status word count for that channel.  The word count is used for
addressing when storing the word as well as for tracking the contents
and overflow status of the queue.

      CE interrupts are generated when a channel detects an error
which will essentially disable that specific channel while having no
anticipated impact on the operation of the remaining 31 channels.
Such conditions usually occur as a result of a RAM parity error which
impacts a region of the address space used only by the interrupting
channel.  As in the case of the EOP, INT will capture associated
status (CE interrupt status word -CEISW) and store it on that
channel's interrupt status queue. Fig. 3 shows the CEISW in more
detail.  Unlike EOP interrupts, the queue for CE interrtpts is only
one deep.  Sance the presence of the CE interrupt will effectively
disable the channel, there is no need to continue queuing subsequent
errors on that channel.

      In addition to these "channelized" interrupts (there are 32
channels, each with two types yielding a total of 64 u...