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Mixed Technology Overvoltage Protection

IP.com Disclosure Number: IPCOM000121662D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+3]

Abstract

The described scheme allows operating > 1 micron CMOS chips (at a power supply of 5 V) and submicron CMOS chips (at a power supply of 3.4 V) on the same bus without any breakdown or reliability problems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mixed Technology Overvoltage Protection

      The described scheme allows operating  > 1 micron CMOS
chips (at a power supply of 5 V) and submicron CMOS chips (at a power
supply of 3.4 V) on the same bus without any breakdown or reliability
problems.

      The development of submicron technology necessitates adapting
the power supply voltage.  The very thin gate oxide and the short
channel of the transistors do not withstand a voltage of 5 V.  For
this reason, the chips involved have to be operated at a voltage of
between 3 and 4 V (the most likely value being 3.4 V + 10 %).
Problems are encountered when the new technology is used in a 5 V
environment where chips built in the new submicron technology have to
communicate with older chips (Fig. 1).  Existing chips are
TTL-compatible, and the most positive up-level (MPUL) of their
drivers is 5.5 V.  Such an MPUL would destroy the input/output
circuits of the new submicron devices, the most allowable up-level
(MAUL) of which is about 4.0 V. Therefore, a circuit scheme is
required which allows the two technologies to communicate without
destroying the more sensitive new chips.

      Protection is needed in the high-impedance state (- Hz = 0) and
when the output of submicron chips is raised to 5.5 V and lowered to
0 from the outside.  At no time, however, must the transistors be
subject to a voltage exceeding 4.0 V.  To avoid destruction, the
circuit is analyzed both statically and dynamically.  In addition,
the output must be free from leakage current in the high-impedance
state.

      The circuit of Fig. 2 shows a CMOS driver circuit operated at
3.6 V and consisting of transistors T1 and T2. This output stage is
protected against an MPUL of 5.5 V of its counterpart (Fig. 1).

      The protection circuit consists of transistors T3 to T12.  The
function of this circuit is described below.
      a.   P...