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Hardware Implemented Program Event Recording

IP.com Disclosure Number: IPCOM000121669D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Getzlaff, K: AUTHOR [+3]

Abstract

The S/370 architecture is provided with program event recording (PER) which interrupts the program when a PER event, such as STORE, writes in a particular memory area. For PER area definition, two addresses PER start and PER end are used. If the PER start address PS is lower than the PER end address PE, then the area between the PER start and the PER end address is defined. Alternatively, if PER start is higher than PER end, the area between the PER start address, the memory max address, the memory address 0, and the PER end address is defined (Fig. 1).

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This is the abbreviated version, containing approximately 52% of the total text.

Hardware Implemented Program Event Recording

      The S/370 architecture is provided with program event
recording (PER) which interrupts the program when a PER event, such
as STORE, writes in a particular memory area. For PER area
definition, two addresses PER start and PER end are used.  If the PER
start address PS is lower than the PER end address PE, then the area
between the PER start and the PER end address is defined.
Alternatively, if PER start is higher than PER end, the area between
the PER start address, the memory max address, the memory address 0,
and the PER end address is defined (Fig. 1).

      PER program interrupts should occur only in response to PER
events.  In addition, the PER events, such as STORE, BRANCH and
INSTRUCTION FETCH, must be readily distinguishable.

      Fig. 2 shows a PER concept which allows several PER events to
be simultaneously triggered and detected according to the number of
bytes involved.  PER event detection proceeds at processor speed
without processor performance degradation.  The hardware required is
minimized by using a common 31-bit memory/instruction/address bus and
a 4-bit instruction address bus.  Only two comparators (- 31 bits)
and 2 comparators (> 4 bits) are required for detecting two
concurrent PER events.  The respective area selected - area 1 or 2,
is determined by subtracting the PER start address from the PER end
address and storing the ALU carry status in a PER carry latch which
is an integral part of the control logic.

      PER STORE and BRANCH events are similarly detected, the
difference being reflected by the effective field length EFL(0..2),
since for a STORE event a memory field is compared with the PER area.
This field is defined by a start and an end address.  The end address
is the start address + EFF(0..2) (Fig. 3).  Thus, the following PER
STORE events may occur.

      Start and end address differ only in the case of a PER STORE
event (EFL/0).  The decoder logic decides whether the status of the
BRANCH or the STORE event is set.  A BRANCH STORE event occurs when
the PER start address(1..31) is inverted and added to address...