Browse Prior Art Database

Host Channel Micro-sequencer

IP.com Disclosure Number: IPCOM000121685D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 128K

Publishing Venue

IBM

Related People

Crandall, DR: AUTHOR [+3]

Abstract

Described is a host channel micro-sequencer facility that provides a programmable and loadable host channel interface which permits corrections to a specific emulation through software updating. The facility also provides different control unit emulations based on a single hardware design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Host Channel Micro-sequencer

      Described is a host channel micro-sequencer facility that
provides a programmable and loadable host channel interface which
permits corrections to a specific emulation through software
updating.  The facility also provides different control unit
emulations based on a single hardware design.

      Attachments to a host channel may provide emulation
capabilities of a specific control unit and may be such that errors
in emulation will require alteration of a product. The concept
described herein provides a means whereby not only corrections to a
specific emulation can be made through a software update, but also
provides the ability to offer different control unit emulations based
on a single hardware design.  This allows a user the flexibility to
use the feature as a terminal controller as well as a high-speed data
mover.

      The figure depicts a functional block diagram of the host
channel micro-sequencer showing how the various elements are
interfaced together.  The following is a short description of the
micro-sequencer elements:
      o    Tag Receiver - A compatible receiver/buffer which passes
inbound tag control lines from the channel to the comparator.
      o    Data Receiver - A compatible receiver/buffer which passes
inbound data lines from the channel to the comparator and/or the
internal data bus.
     o    Tag Driver - A compatible latch/driver which presents tag
control lines to the channel from the host channel micro- sequencer.
      o    Data Driver - A compatible latch/driver which presents
data lines to the channel from the host channel micro-sequencer.
      o    Comparator - A functional element which compares two
sources selected by the sequencer.  The comparison may be for
identity purposes in determining the presence or absence of a
specific bit, the presence or absence of a group of bits, or a direct
result pass or fail operation.  The comparator also provides an
output byte which is the functional result of the operation; an AND
or OR of the input bytes.
      o    Sequencer - A logic element which addresses the writable
control store to obtain an instruction. It selects the source or
sources required for the execution of that instruction, directs the
comparator to perform a required operation, selects the data
destination, if required, and establishes the address of the next
instruction.
      o    Writable control store - A memory area which is externally
loaded.  It provides instructions for the sequencer and an immediate
data byte for those instructions which write a literal to a specified
location.
      o    Emulation memory - A data storage area which provides data
storage for transactions with the channel and to control information
as defined by the software.
      o    Interrupt - An interrupt, or flag, which is provided to
the host channel micro-sequencer through this line and/or an...