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Method of Overrun Protection for 32 Channel Circular Receive Buffer

IP.com Disclosure Number: IPCOM000121689D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 133K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+5]

Abstract

A technique is described wherein 32 channel circular receive buffers with overrun protection during direct memory access (DMA) operation are used by the integrated data link controller (IDLC) chip which handles 32 channels of either LAP-B, LAP-D, or synchronous data link control (SDLC) protocols for integrated services digital network (ISDN) primary rate.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Overrun Protection for 32 Channel Circular Receive Buffer

      A technique is described wherein 32 channel circular
receive buffers with overrun protection during direct memory access
(DMA) operation are used by the integrated data link controller
(IDLC) chip which handles 32 channels of either LAP-B, LAP-D, or
synchronous data link control (SDLC) protocols for integrated
services digital network (ISDN) primary rate.

      Conventionally, telecommunication devices' receive buffer
scheme would require the microcode overhead of programming the DMA at
the beginning and end of buffer addresses each time a buffer is
filled or end of buffer condition is encountered.  The imbedded DMA
controller of the IDLC has a built-in overrun protection mechanism
which prevents the receive buffer from overflowing.  As frames are
received, after undergoing HDLC protocol specific processing, such as
stripping of flags, transparency check, and cyclic redundancy check
(CRC) validity check, data is placed in the memory in a circular
receive buffer for each channel.  When an end of buffer is
encountered, the overrun protection mechanism stops the DMA.  Without
this mechanism, the data already available in the buffer would be
overwritten.

      Fig. 1 illustrates one of the 32 channel circular receive
buffers used by the IDLC.  The LAST_ADDRESS denotes the bottom of the
buffer, FIRST_ADDRESS denotes the top of the buffer,
RCVR_BUFFER_ADDRESS denotes the current address where the received
data is placed, and BOUNDARY_ADDRESS denotes the logical end of
buffer.  The buffer is managed by both the hardware and microcode.
The programmer can select RCVR_BUFFER_ADDRESS to denote the top of
the buffer.  When the DMA controller reaches LAST_ADDRESS it will
automatically begin DMAing at the top of the buffer.  The first
location which the IDLC will begin DMAing to on reception of the new
frame will be on a word (32 bit) input/output processor (IOP) memory
location.  Interrupt notification to the microcode will be sent in
the interrupt status for an 'end of receive frame'.  In addition, a
BOUNDARY_ADDRESS can be programmed to prevent the circular buffer
from being accidentally overwritten by the IDLC when receiving frames
from the network.  If the boundary condition is encountered, the IDLC
will automatically stop DMAing data into the receiver data buffer and
a 'received DMA boundary check' interrupt and status indication will
be generated.

      Notice that the boundary check feature can be disabled by
setting BOUNDARY_ADDRESS to a value of LAST_ADDRESS + 1. Since the
IDLC will never attempt to access an address greater than
LAST_ADDRESS, it will not encounter the BOUNDARY_ADDRESS.

      Fig. 2 shows a set of controlled registers used by the IDLC to
manage the circular receive buffer.  There are 32 sets...