Browse Prior Art Database

Method of Providing Microcode Compatibility Between Microprocessors

IP.com Disclosure Number: IPCOM000121701D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+4]

Abstract

Described is a method to provide microcode compatibility and to increase the performance of data level controllers which use conventional microprocessors, such as the Intel 286 or 386SX* and the Motorola 68000** microprocessors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Providing Microcode Compatibility Between Microprocessors

      Described is a method to provide microcode compatibility
and to increase the performance of data level controllers which use
conventional microprocessors, such as the Intel 286 or 386SX* and the
Motorola 68000** microprocessors.

      The method involves the direct memory access controller (DMAC)
of the interconnection system data network (ISDN) data link
controller (DLC), as used in personal computer systems.  It
distinguishes between data and data control block (DCB) fetches, but
does not rearrange  DCB data structures.

      Since the mechanism used to fetch data and opcodes differs
between the Motorola 68000 and the Intel 386 microprocessors, in
order to allow the same frame placed in sequential memory locations
to be sent from either microprocessor, the concept introduces an
integrated ISDN module (IIM) direct memory access (DMA) controller
which distinguishes between DCB fetches and data fetches in an Intel
subsystem and re-arranges only data stores and fetches in its
internal register, without rearranging the DCB data. The feature
allows the DMA controller to operate in either an Intel or a Motorola
environment.  In effect, the module manages the Intel reverse storage
convention.

      In prior art, solutions to the architectural differences
between the two microprocessors have been performed by rearranging
both the data and the DCB in the DMA controller at the data link
layer.  Although this solves the problem of performance, it does not
address the problem of code portability.  By using the IIM, both the
performance and the microcode aspects are addressed.  The IIM design
has an integrated DMA controller which recognizes which
microprocessor is being executed and distinguishes between 'DATA' and
'DCB' sto...