Browse Prior Art Database

DRAM Sparing Using Shifting Technique

IP.com Disclosure Number: IPCOM000121702D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Coyle, WE: AUTHOR [+5]

Abstract

Disclosed is a memory module sparing scheme based on a shift-right/ shift-left technique. This technique maintains the capability of sparing for any memory module, but provides improved performance and flexibility over more traditional sparing methods.

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DRAM Sparing Using Shifting Technique

      Disclosed is a memory module sparing scheme based on a
shift-right/ shift-left technique.  This technique maintains the
capability of sparing for any memory module, but provides improved
performance and flexibility over more traditional sparing methods.

      Large memory arrays have a high failure rate due to the numbers
of memory modules required for implementation.  To improve the
effective failure rate, spare modules and hardware to logically swap
them into service for failed modules are often included on the memory
arrays. Traditionally, a single spare module is associated with a
bank of memory modules and is connected to sparing logic in such a
way as to be able to participate at any position on the memory bus.
This type of sparing scheme heavily loads the data lines of the spare
module due to the fanout required to connect the spare module to
every position at which it might participate.  This situation
typically causes the spare module to operate slower than the rest of
the memory modules, making it the limiting factor in memory arrays
designed for speed.

      The shift-right/shift-left technique for module sparing is
illustrated in the figure.  On the left is an array of 10 memory
modules: 8 active modules and two spares.  The data lines of the
memory modules are connected to the data bus on the right via the
connection matrix of the sparing logic. In this scheme, the spare
module cannot participate in any position on the memory bus, but only
in one position.  The ex...