Browse Prior Art Database

Scratch Measurement Technique

IP.com Disclosure Number: IPCOM000121707D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Burke, PA: AUTHOR

Abstract

A technique is outlined for obtaining a quantitative measure (depth and number) of scratches on chemical/mechanical polished surfaces of a wafer during semiconductor fabrication.

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Scratch Measurement Technique

      A technique is outlined for obtaining a quantitative
measure (depth and number) of scratches on chemical/mechanical
polished surfaces of a wafer during semiconductor fabrication.

      Current surface scratch monitoring techniques are
time-consuming and unreliable. They include dark field inspection or
the use of defect monitors. Referring to the figure, the ability to
tune a process to be sensitive to scratches of different depths
follows:
      1) Deposit on a monitor wafer approximately 3000 Ao of
tetraethylortho-silicate (TEOS).
      2) Polish wafer until approximately 1000 A o of TEOS remains.
      3) Wafer is now subjected to a chemical highlighting process.
           a. 100:1 HF dip to remove native oxide.
           b. KOH/IPA or other suitable silicon etchant.
           c. HF is used to remove the 1000 Ao of remaining TEOS.
      4) The scratches are now highlighted, and the scratch density
is measured using a standard light-scattering tool.

      The technique is repeatable, reliable, and can be used to show
significant differences between polishing pads, slurries, break-in
procedures and tool set-up.