Browse Prior Art Database

Fabricating One Semiconductor Contact Stud Borderless to Another

IP.com Disclosure Number: IPCOM000121711D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+2]

Abstract

To accommodate future DRAM density considerations (density may require node strap contacts and bit line contacts to overlap), a method is shown for fabricating one contact stud borderless to another so as to maintain electrical isolation.

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This is the abbreviated version, containing approximately 52% of the total text.

Fabricating One Semiconductor Contact Stud Borderless to Another

      To accommodate future DRAM density considerations
(density may require node strap contacts and bit line contacts to
overlap), a method is shown for fabricating one contact stud
borderless to another so as to maintain electrical isolation.

      A contact borderless to a gate is well known; however, one
contact borderless to another is new, i.e., a neighboring contact is
defined, etched, and filled, borderless to an existing contact. The
existing contact requires an etch-resistant sidewall spacer, and
optionally also an etch-resistant cap if the contact material itself
is not etch- resistant. Extensions to this technique include
borderless gate to diffusion contacts and two borderless vias, one
borderless to another.

      A borderless diffusion contact is shown (Fig. 1) borderless to
a node connection defined as the overlap. The basis for isolation
between these two contacts is the sidewall insulation and insulator
cap. Two processing methods are shown to obtain sidewall and top
insulators.
Method 1

      Referring to Fig. 2, after the polysilicon mandrel is applied,
the node contact hole is defined (masked and etched). Oxide or a
similar insulator is deposited conformally and reactive ion etched
(RIE) back to form spacers. Next, the polysilicon strap material is
deposited conformally and recessed back to height "X". It should be
noted that the oxide or nitride mask used to etch the intrinsic
polysilicon mandrel is left in place to serve as a RIE resistant mask
for the polysili...