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Inverted Differential Manchester Encoder/ Decoder

IP.com Disclosure Number: IPCOM000121712D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Graves, SB: AUTHOR [+3]

Abstract

This article describes a technique for implementing the Inverted Differential Manchester (IDM) encoder and decoder.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Inverted Differential Manchester Encoder/ Decoder

      This article describes a technique for implementing the
Inverted Differential Manchester (IDM) encoder and decoder.

      Below is a state diagram for the IDM encoder.  The base clock
for the IDM encoder is eight times the bit rate.
The state machine decode 'X' is the IDM encoder output.  The input
data (logic '0' or logic '1') has to be stabilized at states [7] and
[8].

      The simplified boolean equations of the IDM encoder state
machine are as follows:
A typical implementation of the IDM encoder/decoder is as follows:

      Below is the state diagram for the IDM decoder.
State [06] resets the Received logic data (RxD) latch (RxD = '0'),
State [0E] sets the RxD latch (RxD = '1'),
State [18] sets the error latch that indicates a code violation is
detected.
States [10], [11], [12], [13], [14], [15], [16], [17] are idle
states.
'C2' latch output is the received data clock (RxC).  Valid data from
Valid data can be sampled from the RxD latch at the C2 rising edge
when 'IDLE' (idle states) is inactive.

      The simplified boolean equations of the IDM decoder state
machine are as follows: