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In Line Subcollector Complementary Bipolar Transistors Using Dual EPI Layers

IP.com Disclosure Number: IPCOM000121744D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Tang, DD: AUTHOR

Abstract

Described is an in-line-sub-collector structure with complementary bipolar transistors with dual epi layers that allows individual optimization of NPN and PNP structures, reduces soft error in one transistor and provides larger process latitude.

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This is the abbreviated version, containing approximately 100% of the total text.

In Line Subcollector Complementary Bipolar Transistors Using Dual
EPI Layers

      Described is an in-line-sub-collector structure with
complementary bipolar transistors with dual epi layers that allows
individual optimization of NPN and PNP structures, reduces soft error
in one transistor and provides larger process latitude.

      Typically, complementary bipolar structures show a p++
subcollector stack over the n++ subcollector, resulting in either a
very high resistance p+ subcollector or very little vertical room for
the PNP base.
      The concept described herein provides an in-line-subcollector
structure  that  eliminates  the  above problems  and  allows
optimization  of  each  PNP  and  NPN transistor.  This is done by
placing the subcollector in the same level over  the  first  epi
layer.    The  layers  are isolated,  and  one  of the transistors is
shielded from the substrate carriers which may cause soft errors.
The various fabrication steps are shown in the figure.